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SPECIFICATIONS FOR LCD MODULE
CUSTOMER CUSTOMER PART NO. PACER DISPLAY NO. DESCRIPTION APPROVED BY DATE PCM0802C
PREPARED BY
CHECKED BY
APPROVED BY
Copyright (c) 2006 Pacer PLC
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DOCUMENT REVISION HISTORY: DATE 1999.8. 2005.3. .12 PAGE 4 DESCRIPTION First release Modify the full specification Update the part number system
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1. Module Classification Information 2. Precautions in use of LCD Modules 3. General Specification 4. Absolute Maximum Ratings 5. Electrical Characteristics 6. Optical Characteristics 7. Interface Pin Function 8. Power Supply 9. Contour Drawing & Block Diagram 10. Function Description 11. Character Generator ROM Pattern 12. Instruction Table 13. Timing Characteristics 14. Initializing of LCM 15. Quality Assurance 16. Reliability
Copyright (c) 2006 Pacer PLC
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11
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13
1 Brand PACER DISPLAY 2 Display Type CM Character Type, GM Graphic Type, NONE Custom-made 3 Display Font Characters X Lines / Rows X Columns /Others 4 Model serials no. 5 RoHS compliant: R YES NONE NO M SMT Type 6 IC Package Type
B T G F S P N Y B G W T F S 6 N W S R T F S N D E F S Y B A W G R S COB Type TAB Type COG Type COF Type Special TN Positive TN Negative STN Positive, Yellow Green STN Negative, Blue STN Positive, Gray FSTN Positive FSTN Negative FFSTN Negative Special 6:00,12 12:00, S Special Normal Temperature Wide Temperature Special Reflective Transmissive Transflective Special None LED EL CCFL Special Yellow-green Blue Amber White Green Red Special
7 LCD Mode
8 Viewing direction 9 Temperature range 10 LCD Polarizer Type
11 Backlight Type
12 Backlight Color
13 Internal Code
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!
(1)Avoid applying excessive shocks to the module or making any alterations or modifications to it. (2)Don't make extra holes on the printed circuit board, modify its shape or change the components of LCD module. (3)Don't disassemble the LCM. (4)Don't operate it above the absolute maximum rating. (5)Don't drop, bend or twist LCM. (6)Soldering: only to the I/O terminals. (7)Storage: please storage in anti-static electricity container and clean environment.
"#
$
Item Dimension 8 characters x 2 Lines 79.0 x 44.0 x 10.0 MAX 79.0 x 44.0 x 14.0 MAX 63.0 x 25.0 57.17 x 23.00 1.15 x 1.36 1.23 x 1.44 6.07 x 11.44 7.30 x 11.56 STN 1/16 6 o'clock or 12 o'clock None, YELLOW-GREEN mm mm mm mm mm mm mm mm Unit
Number of Characters Module dimension(No Backlight ) Module dimension(With LED Backlight ) View area Active area Dot size Dot pitch Character size Character pitch LCD type Duty View direction Backlight Type
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%
&
Item
'
(
Symbol VI VDD-VSS VDD-V0 Top Tstr Top Tstr Min -0.3 -0.3 Vdd-13.5 0 -10 -20 -30 Max VDD+0.3 7.0 0 50 60 70 80 Unit V V V
Input Voltage Supply Voltage For Logic Supply Voltage For LCD Standard Temperature LCM Wide Temperature LCM Operating Temp. Storage Temp. Operating Temp. Storage Temp.
)*
Item Supply Voltage For Logic Supply Voltage For LCD Input High Volt. Input Low Volt. Supply Current
+
Symbol VDD-VSS VDD-V0 VIH VIL IDD VDD=5V Forward current =150 mA Number of LED die 2x15= 30 Ta=25 Condition Min 4.5 4.5 0.7 VDD VSS 0.8 1.2 Typ 5.0 4.8 Max 5.5 5.5 VDD 0.3 VDD 2.0 Unit V V V V mA
Supply Voltage of Yellow-green backlight
VLED
3.8
4.1
4.3
V
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,$
Item View Angle Contrast Ratio Response Time
+
Symbol (V) (H) CR T rise T fall Condition CR 2 CR 2 Min -20 -30 3 250 250 Definition of Response Time ( Tr , Tf ) ms ms Typ Max 35 30 Unit deg deg
Definition of Operation Voltage (Vop)
Intensity 100
Selected Wave Non-selected Wave
Non-selected Conition Intensity
Selected Conition
Non-selected Conition
10
Cr Max
Cr = Lon / Loff
100
90
Vop
Driving Voltage(V)
Tr
Tf
[positive type]
[positive type]
Conditions : Operating Voltage : Vop Frame Frequency : 64 HZ Viewing Angle( " ) : 0 " 0 Driving Waveform : 1/N duty , 1/a bias
Definition of viewing angle(CR 2)
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= 0
Pin No. Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VSS VDD V0 RS R/W E DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 LED(+) LED(-) Level 0V 5.0V H/L H/L H,H H/L H/L H/L H/L H/L H/L H/L H/L
.
Description Ground Supply Voltage for logic H: DATA, L: Instruction code H: Read(MPU L Data bit 0 Data bit 1 Data bit 2 Data bit 3 Data bit 4 Data bit 5 Data bit 6 Data bit 7 Anode of LED Backlight Cathode of LED Backlight Module) L: Write(MPU Module) Chip enable signal
(Variable) Operating voltage for LCD
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= 270
l
r
f
b
= 180
= 90
/
,
*
0
!1
SINGLE SUPPLY VOLTAGE TYPE
DUAL SUPPLY VOLTAGE TYPE
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2
3
(4
5
(
3.0
79.0 75.0 63.0[V.A.] 57.17[A.A.]
C L
NO B/L
LED B/L
10.0[MAX.] 5.0 A.5 0 2-R1.25 36.0
14.0[MAX.] 9.0 A.5 0
44.0 A.5 0 34.5 25.0[V.A.] 23.0[A.A.]
C L
C L
2- 2.5 10.2
2.5
4.0
16- 1.0
P2.54X(16-1)=38.1
4.0
1.6 A.1 0 7.30 6.07 1.15 11.56 11.44 1.36
1.6 A.1 0
76.0 84.0 A.5 0
Vdd V0 Vss
CONTROLLER*
E R/W RS DB0 DB7
8
8
LCD PANEL 8X2 CHARACTERS
8
40
*S6A0069 OR EQUIVALENT
0.08
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0.08
.
$
The LCD display Module is built in a LSI controller, the controller has two 8-bit registers, an instruction register (IR) and a data register (DR). The IR stores instruction codes, such as display clear and cursor shift, and address information for display data RAM (DDRAM) and character generator (CGRAM). The IR can only be written from the MPU. The DR temporarily stores data to be written or read from DDRAM or CGRAM. When address information is written into the IR, then data is stored into the DR from DDRAM or CGRAM. By the register selector (RS) signal, these two registers can be selected. RS 0 0 1 1 R/W 0 1 0 1 Operation IR write as an internal operation (display clear, etc.) Read busy flag (DB7) and address counter (DB0 to DB7) Write data to DDRAM or CGRAM (DR to DDRAM or CGRAM) Read data from DDRAM or CGRAM (DDRAM or CGRAM to DR)
Busy Flag (BF) When the busy flag is 1, the controller LSI is in the internal operation mode, and the next instruction will not be accepted. When RS=0 and R/W=1, the busy flag is output to DB7. next instruction must be written after ensuring that the busy flag is 0. Address Counter (AC) The address counter (AC) assigns addresses to both DDRAM and CGRAM
The
Display Data RAM (DDRAM) This DDRAM is used to store the display data represented in 8-bit character codes. Its extended capacity is 80x8 bits or 80 characters. Below figure is the relationships between DDRAM addresses and positions on the liquid crystal display. High bits Low bits Example: DDRAM addresses 4E AC (hexadecimal) AC6 AC5 AC4 AC3 AC2 AC1 AC0
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1
0
0
1
1
1
0
Copyright (c) 2006 Pacer PLC
Display position DDRAM address 1 2 3 4 5 6 7 8
00 01 02 03 04 05 08 09 10 11 12 13
06 07 14 15
-Line by 8 -Character Display
Character Generator ROM (CGROM) The CGROM generate 5x8 dot or 5x10 dot character patterns from 8-bit character codes. See Table 2. Character Generator RAM (CGRAM) In CGRAM, the user can rewrite character by program. For 5x8 dots, eight character patterns can be written, and for 5x10 dots, four character patterns can be written. Write into DDRAM the character code at the addresses shown as the left column of table 1. To show the character patterns stored in CGRAM.
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Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character patterns Table 1.
F o r 5 * 8 d o t c h a ra c te r p a tte r n s C h a ra c te r C o d e s ( D D R A M d a ta ) 7 6 5 4 3 2 1 0 C G R A M A d d re ss 5 H ig h 4 3 2 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C h a r a c te r P a tte r n s ( C G R A M d a ta ) 7 * * * * * * * * * * * * * * * * * 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 C h a r a c te r p a tte r n ( 2 ) C u r s o r p a tte r n C h a r a c te r p a tte r n ( 1 ) C u r s o r p a tte r n
H ig h
Low
0
0
0
0
*0
0
0
0
0
0
0
*0
0
1
Low 00 00 01 01 00010 10 11 11 00 00 01 01 10 00 1 10 11 11 00 00 1 1 1 1 1 1 1 0 0 1 1
H ig h ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** **
Low 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0
0
0
0
0
0
*
1
1
1
*
*
*
F o r 5 * 1 0 d o t c h a r a c te r p a tte rn s C h a ra c te r C o d e s ( D D R A M d a ta ) 7 6 5 4 3 2 1 0 C G R A M A d d re ss 5 H ig h 0 0 0 0 0 0 0 0 1 1 1 1 4 3 2 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 C h a r a c te r P a tte r n s ( C G R A M d a ta ) 7 * * * * * * * * * * * * 6 * * * * * * * * * * * * 5 4 3 0 0 0 0 0 0 0 0 0 * 2 Low 0 0 0 0 0 0 0 0 0 * 0 0 0 0 0 0 0 0 0 * 0 0 0 1 0
H ig h
Low
Low
H ig h *0 *0 * * * * * * * * *0 * *
0
0
0
0
*0
0
0
0
0
0 0 0 0 0 *
C h a r a c te r p a tte r n C u r s o r p a tte r n
: " H ig h "
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+
Table.2
#
,
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&
Instruction Code Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Clear Display 0 0 0 0 0 0 0 0 0 1
Write "00H" to DDRAM and set DDRAM address to "00H" from AC Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed.
Description
Execution time (fosc=270Khz)
1.53ms
Return Home Entry Mode Set Display ON/OFF Control Cursor or Display Shift
0
0
0
0
0
0
0
0
1
1.53ms
0 0
0 0
0 0
0 0
0 0
0 0
0 1
1 D
I/D C
SH B
Assign cursor moving direction and enable the shift of entire display. Set display (D), cursor (C), and blinking of cursor (B) on/off control bit. Set cursor moving and display shift control bit, and the direction, without changing of DDRAM data. Set interface data length (DL:8-bit/4-bit), numbers of display line (N:2-line/1-line)and, display font type (F:5x11 dots/5x8 dots)
39 s 39 s
0
0
0
0
0
1
S/C R/L
39 s
Function Set Set CGRAM Address Set DDRAM Address Read Busy Flag and Address Write Data to RAM Read Data from RAM
0
0
0
0
1
DL
N
F
39 s
0 0
0 0
0 1
1
AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter.
39 s 39 s
AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter.
Whether during internal operation or not can be known by reading BF. The AC6 AC5 AC4 AC3 AC2 AC1 AC0 contents of address counter can also be read.
0
1
BF
0s
1 1
0 1
D7 D7
D6 D6
D5 D5
D4 D4
D3 D3
D2 D2
D1 D1
D0 D0
Write data into internal RAM (DDRAM/CGRAM). Read data from internal RAM (DDRAM/CGRAM).
43 s 43 s
"
"
don't care
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"
(
+
13.1 Write Operation
RS R/W E DB0 to DB7
VIH1 VIL1 VIH1
tAS PWEH
VIH1 VIL1 VIH1
tAH tAH tEf tH
VIL1
VIL1
VIL1
tEr
VIL1
tDSW
VIH1
VIL1
VIL1
VIH1 Valid data
tcycE
VIL1
Ta=25 , VDD=5.0 0.5V Item Enable cycle time Enable pulse width (high level) Enable rise/fall time Address set-up time (RS, R/W to E) Address hold time Data set-up time Data hold time Symbol tcycE PWEH tEr,tEf tAS tAH tDSW tH 0 10 40 10 Min 1200 140 25 Typ Max Unit ns ns ns ns ns ns ns
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13.2 Read Operation
RS R/W E DB0 to DB7
VIH1 VIL1 VIH1 VIL1
tAS PWEH
VIH1 VIL1 VIH1 VIL1
tAH tAH tEf
VIH1
VIH1
tEr
tDDR
VOH1 VOL1* Valid data
tDHR
VOH1 *VOL1
VIL1
tcycE
NOTE: *VOL1 is assumed to be 0.8V at 2 MHZ operation.
Ta=25 , VDD=5.0 0.5V Item Enable cycle time Enable pulse width (high level) Enable rise/fall time Address set-up time (RS, R/W to E) Address hold time Data delay time Data hold time Symbol tcycE PWEH tEr,tEf tAS tAH tDDR tDHR 10 0 10 100 Min 1200 140 25 Typ Max Unit ns ns ns ns ns ns ns
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13.3
V0.
Timing Diagram of VDD Against V0.
Power on sequence shall meet the requirement of Figure 4, the timing diagram of VDD against
VDD
95%
LOGIC SUPPLY VOLTAGE 0V 50ms(typical)
V0
0V LCD SUPPLY VOLTAGE
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%
6(
!
Power on Wait for more than 40 ms after VDD rises to 4.5 V
BF can not be checked before this instruction.
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set 0000 11* *** Wait for more than 39us RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0000 10* *** 00 NF*** *** Wait for more than 39 s RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0000 10 * * * * Function set 00 NF****** Wait for more than 37us RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display ON/OFF control 000000 *** * 00 1DCB*** * Wait for more than 37 s RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Clear 000000 **** **** 00000 1 Wait for more than 1.53ms RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Entry Mode Set 000000 *** * 1 I/D SH * * * * 000 Initialization ends
BF can not be checked before this instruction. BF can not be checked before this instruction. Function set
4-Bit Ineterface
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Power on W for more than 40 ms after VDDrises to 4.5 V ait
BF can not be checked before this instruction.
RS R/WDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set 000011NF** Wait for more than 39us RS R/WDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 000011NF** Wait for more than 37us RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display ON/OFF control 0 0 0 0 0 0 1 BC D Wait for more than 37 s RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Clear 0000000001 Wait for more than 1.53ms RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Entry Mode Set 0 0 0 0 0 0 0 1 I/D S Initialization ends
BF can not be checked before this instruction. Function set
8-Bit Ineterface
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)7
Item
8
Defect Judgment Criterion A)Clear Size: d mm Acceptable Qty in active area d 0.1 Disregard 0.1Screen Cosmetic Criteria
1
Spots
Minor
2
Bubbles in Polarizer
Minor
3 4 5
Scratch Allowable Density Coloration
Minor Minor Minor
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&
8
Content of Reliability Test
Environmental Test Test Item High Temperature storage Low Temperature storage High Temperature Operation Low Temperature Operation High Temperature/ Humidity Storage High Temperature/ Humidity Operation Temperature Cycle Content of Test Endurance test applying the high storage temperature for a long time. Endurance test applying the high storage temperature for a long time. Endurance test applying the electric stress (Voltage & Current) and the thermal stress to the element for a long time. Endurance test applying the electric stress under low temperature for a long time. Test Condition 60 96hrs -10 96hrs 50 96hrs 0 96hrs Applicable Standard ---- ---- ---- ----
Endurance test applying the high 60 ,90%RH temperature and high humidity storage for a 96hrs long time. Endurance test applying the electric stress (Voltage & Current) and temperature / humidity stress to the element for a long time. Endurance test applying the low and high temperature cycle. -10 25 60 30min 5min 1 cycle 30min 50 ,90%RH 96hrs
----
----
-10 /60 10 cycles
----
Mechanical Test Vibration test Endurance test applying the vibration during transportation and using. Constructional and mechanical endurance test applying the shock during transportation. 10~22Hz 1.5mmp-p 22~500Hz 1.5G Total 0.5hrs 50G Half sign wave 11 msedc 3 times of each direction ----
Shock test
----
***Supply voltage for logic system=5V. Supply voltage for LCD system =Operating voltage at 25
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